research

Current Research

  • Energy Effecient Computing
  • Embedded Systems
  • Stochastic Computing
  • Emerging workloads and platforms
  • Secure Infrastructures

Publications

  1. Heterogeneous System Model for Security in E-Health Applications
    Jellen, Isabel, Callenes-Sloan, Joseph, and Fang, Dongfeng
    In Workshop on IOT Enabling Technologies in Healthcare (IOT-Health) - IEEE International Conference on Communications (ICC) 2021
  2. A Dynamic Reconfiguration-based Approach to Resilient State Estimation
    Joss, Annie, Grassbaugh, Austin, Poshtan, Majid, and Callenes, Joseph
    In IEEE International Conference on Cyber Security and Resilience (IEEE-CSR) 2021
  1. Using Power Infrastructures for Wildfire Detection in California
    Erickson, E., Slobodin, R., Poshtan, M., Taufik, T., and Callenes, J.
    In 2020 IEEE Power Energy Society Innovative Smart Grid Technologies Conference (ISGT) 2020
  2. In Depth Exploration of Added Course Expenses on Students of Various Socioeconomic Status
    Danowitz, Andrew, Benson, Bridget, Hummel, Paul, Callenes, Joseph, and McKell, K Clay
    In 2020 IEEE Frontiers in Education Conference (FIE) 2020
  3. Incorporating Diversity and Inclusion in the Computing Classroom
    Bridget Benson, Joseph Callenes, and Malekmohammadi, Amin
    In 2020 ASEE Virtual Annual Conference Content Access 2020
  1. Algorithmic Approaches to Characterizing Power Flow Cyber-Attack Vulnerabilities
    Tuttle, M., Wicker, B., Poshtan, M., and Callenes, J.
    In 2019 IEEE Power Energy Society Innovative Smart Grid Technologies Conference (ISGT) 2019
  2. Repurposing Retired Faculty Laptops to Make Engineering More Accessible
    Danowitz, A., McKell, K. C., Benson, B., Callenes, J., Hummel, P., and Randall, R.
    In 2019 IEEE Frontiers in Education Conference (FIE) 2019
  3. Impact of Cyber-Attacks on Power Grids with Distributed Energy Storage Systems
    Tuttle, M., Poshtan, M., Taufik, T., and Callenes, J.
    In 2019 IEEE International Conference on Communications, Control, and Computing Technologies for Smart Grids (SmartGridComm) 2019
  4. Algorithmic approaches to characterizing power flow cyber-attack vulnerabilities
    Tuttle, Michael, Wicker, Braden, Poshtan, Majid, and Callenes, Joseph
    In 2019 IEEE Power & Energy Society Innovative Smart Grid Technologies Conference (ISGT) 2019
  1. Optimizing energy in a DRAM based hybrid cache
    He, J., and Callenes-Sloan, J.
    In 19th International Symposium on Quality Electronic Design, ISQED 2018, Santa Clara, CA, USA, March 13-14, 2018 2018
  2. Control Flow Checking Optimization Based on Regular Patterns Analysis
    Zhu, Zhiqi, Callenes-Sloan, Joseph, and Schafer, Benjamin Carrion
    In 2018 IEEE 23rd Pacific Rim International Symposium on Dependable Computing (PRDC) 2018
  3. A Machine Learning based Hard Fault Recuperation Model for Approximate Hardware Accelerators
    Taher, Farah Naz, Callenes-Sloan, Joseph, and Schafer, Benjamin Carrion
    In 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC) 2018
  4. Differences in Mental Health between Students in a Jointly Offered Computer Engineering Program and the two Home Departments
    Danowitz, A., Benson, B., Callenes-Sloan, J., and Hummel, P.
    In 2018 IEEE Frontiers in Education Conference (FIE) 2018
  5. Exploring the Relevance and Energy Usage Implications of Fixed Computer Labs in Electrical Engineering Education
    Callenes-Sloan, J., Hummel, P., Danowitz, A., and Benson, B.
    In 2018 IEEE Frontiers in Education Conference (FIE) 2018
  1. TCache: An energy-efficient DRAM cache design
    He, Jiacong, and Callenes-Sloan, Joseph
    In IEEE International Symposium on Circuits and Systems, ISCAS, Baltimore, MD, USA, May 28-31, 2017 2017
  2. Architecting a Novel Hybrid Cache with Low Energy
    He, Jiacong, and Callenes-Sloan, Joseph
    In 2017 26th International Conference on Parallel Architectures and Compilation Techniques (PACT) 2017
  3. A Novel Architecture of Large Hybrid Cache With Reduced Energy
    He, J., and Callenes-Sloan, J.
    IEEE Transactions on Circuits and Systems I: Regular Papers 2017
  4. A software-defined hybrid cache with reduced energy: poster
    He, Jiacong, and Callenes-Sloan, Joseph
    In Proceedings of the 18th ACM/IFIP/USENIX Middleware Conference: Posters and Demos, Las Vegas, NV, USA, December 11 - 15, 2017 2017
  5. Designing large hybrid cache for future HPC systems
    He, Jiacong, and Callenes-Sloan, Joseph
    In Proceedings of the 25th High Performance Computing Symposium, Virginia Beach, VA, USA, April 23 - 26, 2017 2017
  6. A novel architecture of large hybrid cache with reduced energy
    He, Jiacong, and Callenes-Sloan, Joseph
    IEEE Transactions on Circuits and Systems I: Regular Papers 2017
  7. Architecting a novel hybrid cache with low energy
    He, Jiacong, and Callenes-Sloan, Joseph
    In 2017 26th International Conference on Parallel Architectures and Compilation Techniques (PACT) 2017
  1. Towards low overhead control flow checking using regular structured control
    Zhu, Z., and Callenes-Sloan, J.
    In 2016 Design, Automation Test in Europe Conference Exhibition (DATE) 2016
  2. Reducing the energy of a large hybrid cache
    He, J., and Callenes-Sloan, J.
    In 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) 2016
  3. Reducing the energy of a large hybrid cache
    He, Jiacong, and Callenes-Sloan, Joseph
    In 2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016, Monte Carlo, Monaco, December 11-14, 2016 2016
  4. Couture: Tailoring stt-mram for persistent main memory
    Shihab, Mustafa, Zhang, Jie, Gao, Shuwen, Sloan, Josep, and Jung, Myoungsoo
    In 4th Workshop on Interactions of NVM/Flash with Operating Systems and Workloads ({INFLOW} 16) 2016
  5. Reducing the energy of a large hybrid cache
    He, Jiacong, and Callenes-Sloan, Joseph
    In 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) 2016
  1. Hardware Fault Compensation Using Discriminative Learning
    Taher, Farah Naz, and Callenes-Sloan, Joseph
    In 2015 IEEE 21st Pacific Rim International Symposium on Dependable Computing (PRDC) 2015
  2. Hardware Fault Compensation Using Discriminative Learning
    Taher, Farah Naz, and Callenes-Sloan, Joseph
    In 21st IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2015, Zhangjiajie, China, November 18-20, 2015 2015
  1. Algorithm Selection for Error Resilience in Scientific Computing
    Callenes-Sloan, J., and McNamara, H.
    In 2014 IEEE 20th Pacific Rim International Symposium on Dependable Computing 2014
  1. An algorithmic approach to error localization and partial recomputation for low-overhead fault tolerance
    Sloan, Joseph, Kumar, Rakesh, and Bronevetsky, Greg
    In 2013 43rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN) 2013
  2. Towards analyzing and improving robustness of software applications to intermittent and permanent faults in hardware
    Sharma, Ankur, Sloan, Joseph, Wanner, Lucas F, Elmalaki, Salma H, Srivastava, Mani B, and Gupta, Puneet
    In 2013 IEEE 31st International Conference on Computer Design (ICCD) 2013
  1. On software design for stochastic processors
    Sloan, Joseph, Sartori, John, and Kumar, Rakesh
    In Proceedings of the 49th Annual Design Automation Conference 2012
  2. Algorithmic approaches to low overhead fault detection for sparse linear algebra
    Sloan, Joseph, Kumar, Rakesh, and Bronevetsky, Greg
    In IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012) 2012
  1. Stochastic computing: Embracing errors in architecture and design of processors and applications
    Sartori, John, Sloan, Joseph, and Kumar, Rakesh
    In 2011 Proceedings of the 14th International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES) 2011
  2. A numerical optimization-based methodology for application robustification: Transforming applications for error tolerance
    Sloan, Joseph A
    2011
  3. Algorithmic Techniques for Fault Detection for Sparse Linear Algebra
    Sloan, Joseph, Kumar, Rakesh, Bronevetsky, Greg, and Kolev, Tzanio
    In TECHCON 2011
  1. A numerical optimization-based methodology for application robustification: Transforming applications for error tolerance
    Sloan, Joseph, Kesler, David, Kumar, Rakesh, and Rahimi, Ali
    In 2010 IEEE/IFIP International Conference on Dependable Systems & Networks (DSN) 2010
  1. Fluid NMR-performing power/reliability tradeoffs for applications with error tolerance
    Satori, John, Sloan, Joseph, and Kumar, Rakesh
    In Workshop on Power Aware Computing and Systems 2009
  2. Towards scalable reliability frameworks for error prone CMPs
    Sloan, Joseph, and Kumar, Rakesh
    In Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems 2009