research

Large wildfires can cause significant damages to communities and ecosystems. In California in 2018, 87 people were killed, 2 billion acres were burned, and $16.5 billion in costs were incurred by the State. With increased drought and weather variability, this problem is likely only to worsen. In this paper we propose an approach for detecting early onset fires by leveraging equipment already deployed in existing power grid infrastructures, including those that cover remote areas. Our approach is based on the observation that radiated heat from fires quickly results in changes in transmission line temperatures and sag. As the transmission line temperature increase from radiated heat from a fire, the line also expands in length resulting in sag. By monitoring line temperatures and sag, we show that early onset wildfires (e.g. a 50 m2 wildfire) can be detected in less than a minute and up to 120m away from the transmission line.

As power grid control systems become increasingly automated and distributed, security has become a significant design concern. Systems increasingly expose new avenues, at a variety of levels, for attackers to exploit and enable widespread disruptions and/or surveillance. Much prior work has explored the implications of attack models focused on false data injection at the front-end of the control system (i.e. during state estimation) [1]. Instead, in this paper we focus on characterizing the inherent cyber-attack vulnerabilities with power flow. Power flow (and power flow constraints) are at the core of many applications critical to operation of power grids (e.g. state estimation, economic dispatch, contingency analysis, etc.). We propose two algorithmic approaches for characterizing the vulnerability of buses within power grids to cyber-attacks. Specifically, we focus on measuring the instability of power flow to attacks which manifest as either voltage or power related errors. Our results show that attacks manifesting as voltage errors are an order of magnitude more likely to cause instability than attacks manifesting as power related errors (and 5x more likely for state estimation as compared to power flow).

This abstract is for a Full Paper in the category of Innovative Practice. In Electrical and Computer Engineering programs, we are increasingly seeing a digital divide between students who can study and work on assignments 24/7 from powerful laptops, and those students who are forced to rely on the college’s fixed, limited access computer labs to succeed. This paper discusses a proposal to address this problem in a low-to-no cost way at California Polytechnic State University by issuing underprivileged students laptops that have been recently retired from faculty use. The paper looks at the cost implications (and opportunities) of performing a light refurbishment on old faculty units, and provides benchmarks of retired faculty machines against newer faculty laptops across a number of common Electrical Engineering computation tasks.

Power system cyber-attacks today have become a significant design concern. By initiating false commands and/or injecting false data into power grid controls, attackers can perturb a variety of system state and dynamics. With a rapidly evolving energy landscape and aggressive carbon reduction goals in many locations [1], distributed energy storage systems are likely to be broadly deployed in the future. Energy storage can be used for balancing power demands and managing increased variability from solar and wind resources, as well as increasingly widespread electric vehicle charging stations. In this paper, we study the impact of attacks on emerging power grids with widespread energy storage. Based on a theoretical analysis and numerical simulations, we find that grids using widespread storage can lead to increased system vulnerabilities if not managed intelligently. Finally, we propose an approach for managing storage such that the overall grid is more resilient to attacks.

The die-stacking DRAM cache can be used to increase bandwidth and reduce latency compared with conventional DRAM memory. However, energy becomes an inevitable challenge with the increasing size of DRAM cache. STT-RAM with near-zero leakage can be integrated with DRAM cache as a hybrid cache to reduce static energy, but the high write energy of STT-RAM brings another energy challenge. In this paper, we propose a tri-regional hybrid cache that can exploit the advantage of both DRAM and STT-RAM technologies. The asymmetric data access policy is introduced based on the non-uniform read/write property of the different hybrid cache regions. We also propose a prediction table that can reduce the searching energy of the hybrid cache. The results show that our hybrid cache reduces energy by 26% and improves performance by 11% on average compared with previous work.

With the continuous sub-micron process scaling, reliability of integrated circuits has quickly become a first-order design concern. In modern computing systems, transient errors are increasingly likely to corrupt the computation by altering the control flow or sequencing of instructions, leading to catastrophic failures. Prior work on control flow checking provides good coverage but at a high cost. In this paper, by exploring regular control flow patterns found in most applications, we propose the optimization schemes for software signature control flow checking that could reduce the error detection overheads. Specifically, we leverage the fact that most applications have: (1) simple fan-in / fan-out control flow patterns, and (2) most of control flows can be predicted during the compilation stage through static branch prediction heuristics. By exploiting these opportunities, we propose two techniques to reduce the number of inserted codes at common paths and simplify control flow checking of irregular patterns with minimal overheads. Experimental results on a variety of applications demonstrate that our approaches could reduce checking overhead by almost 2.5x on average while leading to similar fault coverage compared to traditional control flow checking.

Continuous pursuit of higher performance and energy efficiency has led to heterogeneous SoC that contains multiple dedicated hardware accelerators. These accelerators exploit the inherent parallelism of tasks and are often tolerant to inaccuracies in their outputs, e.g. image and digital signal processing applications. At the same time, permanent faults are escalating due to process scaling and power restrictions, leading to erroneous outputs. To address this issue, in this paper, we propose a low-cost, universal fault-recovery/repair method that utilizes supervised machine learning techniques to ameliorate the effect of permanent fault(s) in hardware accelerators that can tolerate inexact outputs. The proposed compensation model does not require any information about the accelerator and is highly scalable with low area overhead. Experimental results show, the proposed method improves the accuracy by 50% and decreases the overall mean error rate by 90% with an area overhead of 5% compared to execution without fault compensation.

This Research Work-In-Progress Paper explores potential causes of measured differences in mental health between students in a joint Computer Engineering Program and students in the two home departments (Electrical Engineering and Computer Science). California Polytechnic State University (Cal Poly) currently runs its Computer Engineering Program (CPE) as a joint offering of the Electrical Engineering (EE) and Computer Science and Software Engineering (CSSE) Departments. The curriculum for this program is made up of roughly 50% computer science courses and 50% electrical engineering courses. With the exception of a single senior level capstone course, all CPE courses are also available to (and in many cases required for) students from the two home departments. As a result of this blended curriculum, it has long been assumed that CPE students would have a similar experience and a similar level of mental wellness to their peers in EE and CSSE. A recent study conducted at Cal Poly, however, indicates that CPE students are substantially more likely to screen positive for risk of Serious Mental Illness (SMI) than their peers. This study uses qualitative interviews with CPE, EE, and CSSE students try to determine potential stressors unique to each program. This study also delves into the quantitative survey data to look for population specific trends that may be feeding into this result.

This Research Paper examines the question of whether fixed computer labs are still a necessary or important facet of the Electrical Engineering Laboratory Environment. Large academic computer labs stocked with high performance computing workstations have long been a major feature of Electrical and Computer Engineering programs. Historically they have been used throughout the curriculum for everything from running complex image processing algorithms in Matlab to simulating and synthesizing advanced digital designs with CAD tools like Vivado. As the cost of computation has declined, however, and as students increasingly bring their own high performance computing devices to the lab, it is no longer clear that workstation-based computer labs provide a significant benefit for student learning. This paper explores this topic by looking at student in-lab computer usage patterns and preferences for an introductory digital design course at California Polytechnic State University San Luis Obispo. Our research also quantifies the potential environmental savings institutions can achieve by moving away from workstation-based labs by comparing average energy usage from students using lab computers versus those using their own laptops.

Emerging die-stacked DRAM cache provides high bandwidth and low latency to break the memory wall. However, energy becomes a major challenge with the increasing size of die-stacked DRAM cache. It is observed that DRAM cache with longer bitlines consumes more energy due to larger capacitance. To reduce the high energy of long bitlines, we propose the TCache by partitioning every subarray of DRAM cache banks into three sublevels and schedule energy-efficient data movement among these levels based on reuse distance. We propose LevelMap and WayMap indicating in which sublevel and way that every data block of DRAM cache is located. Evaluations show these techniques can efficiently reduce energy consumption by 33.4% and improve performance by 10.6% on average.

To handle the memory wall problem and satisfy the high processing speed of the multicore processors, there is significant demand for a large cache capacity in future. The 3D die-stacking DRAM cache with high density can be used as a large cache compared with conventional SRAM cache. However, energy becomes an inevitable challenge with the increasing size of DRAM cache. STT-RAM with near-zero leakage can be integrated with DRAM cache as a hybrid cache to reduce static energy, but the high write energy of STT-RAM brings another energy challenge. We observe that volatile STT-RAM can be utilized in the hybrid cache as a buffer to balance the high static energy of DRAM and the high dynamic energy of non-volatile STT-RAM.

Energy becomes an inevitable challenge when using a large die-stacking dynamic random access memory (DRAM) cache. Although emerging spin-transfer-torque-RAM (STT-RAM) technology can efficiently reduce the static energy of large cache, it cannot completely replace DRAM cache due to the high write energy of STT-RAM. Recently, researchers have observed that there are many redundant bits written in the row buffer and futile bits written back to STT-RAM cells, which do not change the cells’ value but still cost high write energy. In this paper, we first design a large hybrid cache architecture with the DRAM region and the STT-RAM region to reduce the high static energy of DRAM cache. The selective write back to row buffer and selective write back to cell array optimizations are proposed to reduce high write energy of the STT-RAM region by removing the unnecessary bit-writes. Furthermore, we propose reuse distance-oriented data movement to reduce write operations in the STT-RAM region. Finally, we propose a novel tag design for the hybrid cache by moving all tag arrays to the STT-RAM region. The SPEC CPU2006 benchmarks show an average 28.3% energy reduction and 6.7% performance improvement for the write optimizations and 7.3% energy savings and 27.5% instructions per cycle speedups for the proposed tag design.

With process scaling and the adoption of post-CMOS technologies, reliability has been brought to the forefront of modern computer system design. Among the different ways that hardware faults can manifest in a system, errors related to the control flow of a program tend to be the most difficult to handle when ensuring reliable computing. Errors in the sequencing of instructions executed are usually catastrophic, resulting in system hangs, crashes, and/or corrupted data. For this reason, conventional approaches rely on some form of general redundancy for detecting or recovering from a control flow error. Due to the power constraints of emerging systems however, these types of conservative approaches are quickly becoming infeasible. Control Flow Checking by Software Signatures (CFCSS) is a software-based technique for detecting control flow errors [1] that using assigned signatures rather than by using general redundancy. Unfortunately, the performance overhead for CFCSS can still be as high as 80%-90% for many applications. In this paper, we propose a novel method for reducing the overhead of control flow checking by exploiting the regular control structure found in many applications. Specifically, we observe that the alternating sequence of conditional and unconditional based control allows for the full control signatures to be computed at alternating basic blocks. Based on experimental results of the proposed approach, we observe that the overheads of the traditional methods are reduced on average by 25.9%.

Energy is quickly becoming an inevitable challenge to using a large die-stacking DRAM cache. Emerging STT-RAM technology can efficiently reduce the static energy of large cache. However, STT-RAM which has high write energy and latency is not suitable to completely substitute for on-die DRAM cache. We observe that there are a large number of redundant bits written in the row buffer and futile bits written back to STT-RAM cells, which do not actually change the cells’ value but still cost write energy. We utilize this opportunity to reduce energy by removing the unnecessary bit-writes to the STT-RAM cache. In this paper, we design a large hybrid cache architecture with a DRAM region and STT-RAM region. Selective Write Back to Row Buffer and Selective Write Back to Cell Array optimizations are proposed to reduce high write energy of STT-RAM region by comparing write data and existing data in advance. Also, we propose Reuse Distance Oriented Data Movement to reduce write operations in STT-RAM region. The results show our hybrid cache can achieve up to a 28.3% energy reduction and 6.7% performance improvement.

With process scaling and the adoption of postCMOS technologies, permanent faults are becoming a fundamental problem. Circuits containing defects are either discarded (reducing yield) or partially disabled (reducing performance). In this paper, we propose a general approach using supervised and discriminative learning techniques to compensate for the effect of permanent faults on a circuit’s output. The insight for this approach is that many emerging systems and applications are able to tolerate some loss of quality in their computed results. Therefore, more scalable and lower overhead compensation techniques may be used to approximately correct for the effect of hardware faults on the circuit output. The proposed approach is shown to improve the output quality of complex accelerator and application-specific logic by 2-3 orders of magnitude while incurring <;10% area overhead and <;3% performance overhead.

With process scaling and the adoption of post-cmos technologies, reliability and power are becoming a significant concern for future computing systems, especially highly parallel systems. Previous approaches have investigated augmenting applications with additional logic to detect and correct errors efficiently. In this research, we investigate the impact of different algorithmic designs on error resilience and propose an approach for algorithm selection for a class of equations, i.e. partial differential equations (PDEs), that are at the core of many scientific computing applications, which drive HPC systems. Many different schemes have been devised for the approximation of PDE systems, each with different accuracy, stability, and performance properties. In this research, there are two primary questions that we address: (1) Does numerical stability translate to error resilience? and (2) How do we design schemes to improve error resilience? If an algorithm’s error resilience is correlated with its numerical stability properties, this may allow us to design more resilient applications by leveraging well established information on numerical stability. Even with a clear translation of numerical stability to error resilience properties, the question of designing these algorithms still remains however, due to the variety of implementations, schemes, and largely input specific nature of the design. In this research, we propose one approach for automated design using machine-learning. We observe that intelligent selection of the algorithm or a given problem, improves robustness by 20%-50%, on average, over the traditional selection of algorithms, without the addition of any other detection/correction logic.